1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and more specifically relates to a thin film magnetic memory device having a redundancy configuration for repairing a defective memory cell.
2. Description of the Background Art
Attention has been paid to an MRAM (Magnetic Random Access Memory) device as a memory device capable of storing nonvolatile data with lower consumption power. The MRAM device is a memory device which stores nonvolatile data using a plurality of thin film magnetic elements formed on a semiconductor integrated circuit and which can randomly access the respective thin film magnetic elements.
In recent years, it has been made public that the performance of the MRAM device surprisingly advances particularly by using a thin film magnetic body using a magnetic tunnel junction (MTJ) as a memory cell.
FIG. 11 is a schematic diagram showing the configuration of a memory cell having a magnetic tunnel junction (which memory cell will be also referred to simply as xe2x80x9cMTJxe2x80x9d memory cell hereinafter).
Referring to FIG. 11, MTJ memory cell includes a tunneling magneto-resistance element TMR having electric resistance changing according to storage data level, and an access element ATR for forming the path of a sense current Is which passes through tunneling magneto-resistance element TMR during data read. Since access element ATR is typically formed out of a field effect transistor, access element ATR will be also referred to as xe2x80x9caccess transistor ATRxe2x80x9d hereinafter. Access transistor ATR is connected between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).
FIG. 12 is a conceptual view for explaining data read from an MTJ memory cell.
Referring to FIG. 12, tunneling magneto-resistance element TMR includes a ferromagnetic layer FL which has a fixed, uniform magnetization direction (which layer will be also referred to simply as xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter) and a ferromagnetic layer VL which is magnetized in a direction according to an externally applied magnetic field (which layer will be also referred to simply as xe2x80x9cfree magnetic layerxe2x80x9d hereinafter). A tunneling barrier (tunneling film) TB formed out of an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as or the opposite direction to the magnetization direction of fixed magnetic layer FL in accordance with the level of written, stored data. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
During data read, access transistor ATR is turned on in accordance with the activation of a word line WL. As a result, sense current Is can be fed to a current path from a bit line BL to tunneling magneto-resistance element TMR, access transistor ATR and a ground voltage Vss.
The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, if the magnetization direction of fixed magnetic layer FL is the same as (parallel to) that of free magnetic layer VL, the electric resistance of tunneling magneto-resistance element TMR becomes lower than that of tunneling magneto-resistance element TMR if the magnetization direction of fixed magnetic layer FL is opposite (anti-parallel) to that of free magnetic layer FL.
Accordingly, if free magnetic layer VL is magnetized in one of the two directions in accordance with stored data, the voltage change of tunneling magneto-resistance element TMR caused by sense current Is differs according to the level of the stored data. Therefore, if bit line BL is precharged with a constant voltage and then sense current Is is fed to tunneling magneto-resistance element TMR, it is possible to read the data stored in the MTJ memory cell by detecting the voltage of bit line BL.
FIG. 13 is a conceptual view for explaining a data write operation for writing data to the MTJ memory cell.
Referring to FIG. 13, during data write, word line WL is inactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in a direction according to written data is fed to a write digit line WDL and a bit line BL, respectively. The magnetization direction of free magnetic layer VL is determined according to data write currents fed to write digit line WDL and that fed to bit line BL, respectively.
FIG. 14 is a conceptual view for explaining the relationship between the data write current and the magnetization direction of tunneling magneto-resistance element TMR during data write to the MTJ memory cell.
Referring to FIG. 14, a horizontal axis H (EA) indicates a magnetic field applied in an easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. A vertical axis H (HA) indicates a magnetic field applied in a hard axis (HA) direction in free magnetic layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields generated by currents fed to bit line BL and write digit line WDL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL, and free magnetic layer VL is magnetized in the parallel direction or anti-parallel (opposite) direction to the magnetization direction of fixed magnetic layer FL along the easy axis direction in accordance with the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the stored data. In the specification, the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetization directions of free magnetic layer VL will be denoted by Rmax and Rmin (where Rmax greater than Rmin) hereinafter, respectively. The MTJ memory cell can store 1-bit data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in accordance with one of these two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only if the sum of applied magnetic fields H(EA) and H(HA) reaches a region outside of an asteroid characteristic line shown in FIG. 14. Namely, if the applied data write magnetic fields have intensity corresponding to a region inside of the asteroid characteristic line, the magnetization direction of free magnetic layer VL has no change.
As shown in the asteroid characteristic line, if a magnetic field in the hard axis (HA) direction is applied to free magnetic layer VL, it is possible to decrease a magnetic threshold value necessary to switch the magnetization direction along the easy axis.
If operation points during data write are designed as shown in the example of FIG. 14, the data write magnetic field in the easy axis direction is designed to have an intensity of HWR in the data write target MTM memory cell. That is, the value of the data write current fed to bit line BL or write digit line WDL is designed so as to obtain this data write magnetic field HWR. Generally, data write magnetic field HWR is expressed by the sum of a switching magnetic field HSW necessary to change over a magnetization direction and a margin xcex94H. That is, data write magnetic field HWR is expressed by HWR=HSW+xcex94H.
To rewrite the data stored in the MTJ memory cell, i.e., to rewrite the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to feed a data write current at not lower than predetermined level to each of write digit line WDL and bit line BL. By doing so, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the parallel or opposite (anti-parallel) direction to the magnetization direction of fixed magnetic layer FL in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction, i.e., the stored data of the MTJ memory cell which has been written to tunneling magneto-resistance element TMR is held in a nonvolatile manner until new data is written.
Normally, a memory device includes a redundant configuration for repairing a normal memory cell to which a defect occurs (which memory cell will be also referred to as xe2x80x9cdefective memory cellxe2x80x9d hereinafter) in addition to a plurality of normal memory cells selectively accessible according to an access signal.
FIG. 15 is a schematic block diagram which shows the configuration of a conventional MRAM device including a redundant configuration. In FIG. 15, the configuration related to data read, of such an MRAM device is typically shown.
Referring to FIG. 15, the conventional MRAM device includes a memory array MA in which a plurality of normal memory cells MC and spare memory cells SMC for repairing defective memory cells are arranged in a matrix, a row select circuit RDC and a column select circuit CDC.
In memory array MA, a plurality of spare memory cells SMC are arranged to constitute a spare row. In FIG. 15, normal memory cells MC arranged in 4 rowsxc3x974 columns and spare memory cells SMC arranged in 1 rowxc3x974 columns are shown by way of example. A spare word line SWL and word lines WL0 to WL3 are arranged to correspond to the row of the spare memory cells and the rows of the normal memory cells, respectively. Namely, in the MRAM device shown in FIG. 15, a defective memory cell is replaced and relieved in units of a defective memory cell row including the defective memory cell.
On the other hand, spare memory cells SMC and normal memory cells MC are arranged so that each memory cell column is shared among SMC and MC. Bit lines BL0 to BL3 are arranged to correspond to the memory cell columns, respectively. Sense amplifiers SA0 to SA3 are provided to correspond to bit lines BL0 to BL3, respectively. Sense amplifiers SA0 to SA3 amplify data transmitted through bit lines BL0 to BL3, respectively.
Row select circuit RDC stores redundant information including information which indicates the presence/absence of a defective memory cell, i.e., whether or not the spare row is used and information for specifying the defective memory cell, and executes row selection in accordance with the redundant information and inputted row addresses RA0 and RA1.
Column select circuit CDC executes column selection in accordance with inputted column addresses CA0 and CA1, and outputs data, read from one of bit lines BL0 to BL3 corresponding to the selected column, to an external I/O (EI/O) provided to execute the transmission and receiving of data to and from the outside of the MRAM device.
FIG. 16 is a circuit diagram which shows the configuration of row select circuit RDC.
Referring to FIG. 16, row select circuit RDC includes a spare decoder SD and row select gates RLG0 to RLG3 which constitute a normal row decoder.
Spare decoder SD includes fuse elements FS0 to FS2 for storing information used for redundancy repair in a nonvolatile manner. Fuse elements FS0 and FS1 store the levels of row addresses RA0 and RA1 for showing the defective memory cell row, respectively. Fuse element FS2 stores information which indicates whether or not the spare row is used.
Each of fuse elements FS0 to FS2 is programmed by the cut off (blow) of the fuse element in accordance with the input of a laser beam or the like. Namely, each fuse element FS can hold 1-bit information in a nonvolatile manner in accordance with a blown state (cut off state) or a non-blown state (conductive state).
Spare decoder SD includes a latch circuit LT0 which latches a voltage according to the state of fuse element FS0 to a node Ng0, a latch circuit LT1 which latches a voltage according to the state of fuse element FS1 to node Ng1, and a transistor 100 which pulls up each of nodes Ng0 and Ng1 to a power supply voltage Vcc. In each of latch circuits LT0 and LT1, the driving force of an inverter having node Ng0 or Ng1 as an input side is designed to be higher than the driving force of transistor 100.
Spare decoder SD also includes transistor gates 101 and 102 provided between nodes to which row addresses RA0 and/RA0 (at inverted level of that of RA0) are transmitted and a node Ns0, respectively, and transistor gates 103 and 104 provided between nodes to which row addresses RA1 and/RA1 (at inverted level of that of RA1) are transmitted and a node Ns1, respectively. Each of transistor gates 101 to 104 consists of, for example, an N-channel MOS transistor.
Spare decoder SD further includes a P-channel MOS transistor 105 which is connected between power supply voltage Vcc and a node Ns2, and N-channel MOS transistors 106, 107 and 108 which are connected in series between node Ns2 and ground voltage Vss.
The gate of transistor 105 is coupled to ground voltage Vss. The gate of transistor 106 is connected to node Ns0 and that of transistor 107 is connected to node Ns1. The gate of transistor 108 is coupled to power supply voltage Vcc through fuse element FS2. An inverter 109 drives spare word line SWL in accordance with the inverted voltage level of node Ns2.
The operation of spare decoder SD will next be described.
If no defective memory cell exists in the normal memory cells, i.e., the spare row is not used, then fuse element FS2 is blown and turned into a cut off state. In this state, transistor 108 is always set to be turned off, so that the voltage of node Ns2 is fixed to power supply voltage Vcc (H level). As a result, spare word line SWL is kept to be in an inactive state (ground voltage Vss: L level).
In the specification, high voltage level (e.g., power supply voltage Vcc) corresponding to xe2x80x9c1xe2x80x9d and low voltage level (e.g., ground voltage Vss) corresponding to xe2x80x9c0xe2x80x9d, where xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are binary voltage levels of data, a signal, a signal line and the like, will be also referred to simply as xe2x80x9cH levelxe2x80x9d and xe2x80x9cL levelxe2x80x9d, respectively.
On the other hand, if the spare row is used to replace a defective memory cell, the fuse element FS2 is kept to be in conductive state and the levels of row addresses RA0 and RA1 which indicate the defective memory cell row are programmed by fuse elements FS0 and FS1.
If fuse element FS0 is in a cut off state, node Ng0 is set at power supply voltage Vcc (H level) by transistor 100. In response to this setting, transistor 101 is turned on and transistor gate 102 is turned off. Due to this, when row address RA0=xe2x80x9c1xe2x80x9d, transistor 106 is turned on and when row address RA0=xe2x80x9c0xe2x80x9d, transistor 106 is turned off.
If fuse element FS0 is in conductive state, node Ng0 is set at L level (ground voltage Vss). In response to this setting, transistor 102 is turned on while transistor 101 is turned off. Due to this, when row address RA0=xe2x80x9c0xe2x80x9d, transistor 106 is turned on and when row address RA0=xe2x80x9c1xe2x80x9d, transistor 106 is turned off.
In this way, if fuse element FS0 is in a cut off state and row address RA0 is xe2x80x9c1xe2x80x9d (at H level), transistor 106 is turned on. If fuse element FS0 is in a conductive state and row address RA0 is xe2x80x9c0xe2x80x9d (at L level), transistor 106 is turned off. In other words, transistor 106 can be turned on in accordance with the predetermined level of row address RA to correspond to the state of row address RA0 programmed by fuse element FS0.
Likewise, fuse element FS1, latch circuit LT1, transistor gates 103 and 104 and transistor 107 are provided for row address RA1 as in the case of fuse element FS0, latch circuit LT0, transistor gates 101 and 102 and transistor 106 provided for row address RA0.
Therefore, transistor 107 is turned on in response to the predetermined level of row address RA1 to correspond to the state of row address RA1 programmed by fuse element FS1.
If row address RA0 corresponding to the defective memory cell row is xe2x80x9c1xe2x80x9d, fuse element FS0 is turned into a cut off state and if row address RA0 is xe2x80x9c0xe2x80x9d, fuse element FS0 is turned into a conductive state, whereby row address RA0 which indicates the defective memory cell row can be programmed. Likewise, row address RA1 corresponding to the defective memory cell row can be programmed by fuse element FS1.
According to such a configuration of spare decoder SD, if fuse element FS2 is not blown but is in the conductive state and the row addresses of the defective memory cell row programmed by fuse elements FS0 and FS1 are consistent with inputted row addresses RA0 and RA1, respectively, then spare word line SWL is driven to H level and thereby activated.
The activation of word lines WL0 to WL3 corresponding to the normal memory cell rows is controlled by row select gates RLG0 to RLG3, respectively.
Row select gate RLG0 controls the activation of word line WL0 in accordance with an AND operation result for the voltage levels of row addresses/RA0 and/RA1 and node Ns2. Word line WL0 is, therefore, activated to H level if node Ns2 is at L level (i.e., spare word line SWL is in the inactive state), RA0=xe2x80x9c0xe2x80x9d and RA1=xe2x80x9c0xe2x80x9d.
Likewise, row select gate RLG1 controls the activation of word line WL1 in accordance with an AND operation result for the voltage levels of row addresses/RA0 and RA1 and node Ns2. Word line WL1 is, therefore, activated to H level if spare node line SWL is inactive, RA0=xe2x80x9c0xe2x80x9d and RA1=xe2x80x9c1xe2x80x9d.
Row select gate RLG2 controls the activation of word line WL2 in accordance with an AND operation result for the voltage levels of row addresses RA0 and/RA1 and node Ns2. Word line WL2 is, therefore, activated to H level if spare word line SWL is inactive, RA0=xe2x80x9c1xe2x80x9d and RA1=xe2x80x9c0xe2x80x9d.
Row select gate RLG3 controls the activation of word line WL3 in accordance with an AND operation result for the voltage levels of row addresses RA0 and RA1 and node Ns2. Word line WL3 is, therefore, activated to H level if spare word line SWL is inactive, RA0=xe2x80x9c1xe2x80x9d and RA1=xe2x80x9c1xe2x80x9d.
By adopting such a configuration, if spare word line SWL is activated, each of word lines WL0 to WL3 is inactivated to L level. If spare word line SWL is inactive, one of word lines WL0 to WL3 is selectively activated in response to a combination of row addresses RA0 and RA1.
According to the MRAM device shown in FIG. 15, therefore, it is possible to replace and repair a defective memory cell in the normal memory cells by the spare row consisting of spare memory cells SMC.
As described above, to realize the redundant configuration, the conventional MRAM device is required to include fuse elements which are cut off (blown) in response to the input of a laser beam or the like. This, in turn, requires a special equipment such as a laser trimming device and requires a processing step therefor, disadvantageously increasing time and cost required for a programming processing. Further, since each fuse element has a relatively large area, the area of the MRAM device is thereby disadvantageously increased. Besides, if external input such as laser irradiation causes physical destruction, other necessary circuits are disadvantageously damaged and the operation reliability of the overall MRAM device may possibly be deteriorated.
It is an object of the present invention to provide a configuration of a thin film magnetic memory device capable of programming information necessary for redundancy repair using the same magnetic storage element as a normal memory cell used for data storage.
In short, the present invention provides a thin film magnetic memory device which includes a memory array, a plurality of program units, a program information read portion, and a select circuit. In the memory array, a plurality of normal memory cells and a plurality of spare memory cells each for replacing and repairing a defective memory cell in the plurality of normal memory cells are arranged in a matrix. Each of the plurality of program units stores redundant information of 1 bit used for replacing the defective memory cell. The program information read section reads the redundant information from the plurality of program units before executing a data read operation. The select circuit controls access to the plurality of normal memory cells and the plurality of spare memory cells in accordance with the redundant information read by the program information read portion and an inputted address signal. Each of the program units includes two program cells each having a same configuration as a configuration of each of the normal memory cells and the spare memory cells, and the two program cells store data at different levels, respectively.
Therefore, a main advantage of the present invention is in that it is possible to store the redundant information in a nonvolatile manner without providing any fuse elements, by using program cells each of which is the same in configuration as the normal memory cells and the spare memory cells and each of which is formed to have a small area. As a result, it is possible to magnetically write data as in the case of normal data write without requiring a special processing step and a dedicated equipment and without causing physical destruction. Consequently, it is possible to program the redundant information without causing the increase of processing time and processing cost and further without any risk of deteriorating the operation reliability of the entire device.
It is preferable that the program information read section includes a power-ON detection circuit for detecting whether the thin film magnetic memory device is turned on, and a plurality of program information read units for reading the redundant information from a plurality of program cells for a predetermined period after the thin film magnetic memory device is turned on. The select circuit preferably includes a latch circuit for holding the redundant information read from the plurality of program units while the thin film magnetic memory device is turned on.
As a result, since it is possible to obtain the redundant information only by causing a data read current to pass through the program cells only for a relatively short period right after the thin film magnetic memory device is turned on, it is possible to suppress the occurrence of program cell failure and to improve operation reliability.
According to another aspect of the present invention, there is provided a thin film magnetic memory device which includes a memory array, a plurality of data lines, a data read circuit and a select circuit. In the memory array, plurality of normal memory cells, a plurality of spare memory cells for replacing and repairing a defective memory cell in the plurality of normal memory cells, and a plurality of program cells for storing redundant information used for replacing the defective memory cell are arranged in a matrix. The data lines are each shared among the plurality of normal memory cells, the plurality of spare memory cells and the plurality of program cells. The data read circuit reads data from the plurality of normal memory cells, the plurality of spare memory cells and the plurality of program memory cells through the data lines. The select circuit includes a latch circuit holding the redundant information read by the data read circuit from the plurality of program units before executing a data read operation. The select circuit controls access to the plurality of normal memory cells and the plurality of spare memory cells in accordance with an address signal and the redundant information held in the latch circuit.
According to the thin film magnetic memory device constituted as described above, it is possible to store the redundant information in a nonvolatile manner without providing any fuse elements, by using program cells each of which is the same in configuration as the normal memory cells and the spare memory cells and each of which is formed to have a small area. In addition, since it is unnecessary to separately provide a dedicated circuit for reading the redundant information from the program cells, it is possible to reduce circuit area. Further, since it is possible to obtain the redundant information only by causing a data read current to pass through the program cells only for relatively a short period right after the thin film magnetic memory device is turned on, it is possible to suppress the occurrence of program cell failure and to improve operation reliability.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.